This invention pertains to methods of making articles that comprise an oxide layer on a GaAs-based semiconductor body, typically GaAs-based field effect transistors (FETs), and integrated circuits comprising such FETs.
GaAs-based transistors and circuits are used in, for instance, wireless communication apparatus, high speed logic ICs and high power microwave devices, due inter alia to the relatively high electron mobility in GaAs, and the availability of semi-insulating GaAs substrates.
Early devices suffered from poor gate oxide/GaAs interface quality, including a high density of interface states. In recent years, substantial effort has been directed at this problem. For instance, U.S. Pat. No. 5,451,548 discloses formation of a Ga2O3 film on GaAs by e-beam evaporation from a high purity single crystal of Gd3Ga5O12.
U.S. patent application Ser. No. 09/093,557 discloses articles (e.g., a GaAs-based MOS-FET) that comprises an oxide of overall composition GaxAyOz, where A is an element adapted for stabilization of Ga in the 3+ oxidation state, x is greater than or equal to zero, y/(x+y) is greater than 0.1, and z is selected to satisfy the requirement that both Ga and A are substantially fully oxidized.
The above-referenced ""558 patent application discloses a method of making a GaAs-based MOS-FET that comprises a gate oxide layer of overall composition GaxAyOz, as defined above. The method comprises formation of the gate oxide layer subsequent to implant activation and other process steps, with no high temperature (e.g.,  greater than 700xc2x0 C.) processing being carried out subsequent to gate oxide formation.
The method of the ""558 patent application, however, has been found to have shortcomings. In particular, the yield of acceptable devices is relatively low. Furthermore, and in common with other prior art GaAs-based metal/insulator/semiconductor FETs, devices made according to the ""558 patent application exhibit significant hysteresis of the drain current/voltage characteristic, and also exhibit significant decrease of the drain current with time, resulting in devices frequently having unacceptably short life time. See, for instance, Y-H Jeong, IEEE Electron Device Letters, Vol. 15(7), p. 251 (1994), especially FIGS. 3 and 4. The reference discloses a 22% decrease of drain current over a period of 104 s, and states that the disclosed MISFETs exhibit xe2x80x9c. . . the best performance among the accumulation mode GaAs MISFETs.xe2x80x9d Clearly, for commercial use of GaAs-based MOS-FETs, the above referred-to hysteresis and decrease with time will have to be substantially eliminated.
In view of the potential advantages of GaAs-based MOS devices, it would be highly desirable to have available a method of making such devices that gives improved device yield. This application discloses such a method. The method also can produce MOS-FETs that are substantially free of drain current hysteresis, and that are also substantially free of drain current drift with time, and thus have long lifetime.
Embodiments of the invention comprise forming an insulator layer (typically but not necessarily an oxide layer) on a GaAs-based semiconductor surface. Just prior to the start of insulator formation the semiconductor surface is substantially atomically clean and substantially atomically ordered. The semiconductor surface typically is a (100) surface.
Herein a semiconductor surface is considered to be xe2x80x9csubstantially atomically cleanxe2x80x9d if surface coverage by impurity atoms is less than (typically substantially less than) 1% of a monolayer, preferably less than 0.1% of a monolayer. The degree of coverage by impurity atoms can be measured by a known technique (XPS). See, for instance, P. Pianetta et al., Phys. Rev. Letters, Vol. 35 (20), p. 1356 (1975).
A GaAs-based (100) semiconductor surface herein is considered to be xe2x80x9csubstantially atomically orderedxe2x80x9d if the surface exhibits a clean 2xc3x974 (or possibly 4xc3x976 or other) RHEED (reflection high energy electron diffraction) pattern. Methods that can be used to produce a substantially atomically ordered (100) GaAs surface are known, as are techniques for producing a substantially atomically clean (100) GaAs surface. A GaAs surface that is substantially atomically clean and substantially atomically ordered is frequently referred to as a xe2x80x9creconstructedxe2x80x9d surface.
The instant invention exemplarily is embodied in a method of making an article (e.g., an IC, or a personal communication device that comprises the IC) that comprises a GaAs-based MOS-FET having improved characteristics, including a low gate oxide/semiconductor midgap interface state density.
More specifically, the invention exemplarily is embodied in a method of making an article that comprises a GaAs-based MOS-FET comprising a GaAs-based substrate having a major surface, two spaced apart regions of a first conductivity type extending from the major surface into the substrate (designated xe2x80x9csourcexe2x80x9d and xe2x80x9cdrainxe2x80x9d, respectively), a metal contact disposed on each of said source and drain, with an oxide layer (designated xe2x80x9cgate oxidexe2x80x9d) disposed on the major surface between the source and the drain, and with a gate metal contact disposed on the gate oxide layer.
The MOS-FET advantageously is a planar device (i.e., the semiconductor surface is planar, without etched recesses or epitaxial regrowth), the source and drain regions extend into the GaAs-based material of a second conductivity type, associated with the gate oxide/semiconductor interface is a midgap interface state density of at most 1011 cmxe2x88x922 eVxe2x88x921.
The gate oxide layer typically but not necessarily has overall composition GaxAyOz, where Ga substantially is in a 3+ oxidation state, where A is one or more electropositive stabilizer element for stabilizing Ga in the 3+ oxidation state, x is greater than or equal to zero, y/(x+y) is greater than or equal to 0.1, and z is sufficient to satisfy the requirement that Ga and A are substantially fully oxidized. Herein, Ga and A each are considered to be xe2x80x9csubstantially fully oxidizedxe2x80x9d if at least 80% (preferably at least 90%) of the respective element is fully oxidized, i.e., is in the highest oxidation state of the element. The highest oxidation state of Ga is 3+. The highest oxidation state of A depends on A. For instance, if A is an alkaline earth, then the state is 2+, and if A is Sc, Y, or a rare earth element, then the state is frequently, but not always, 3+.
The method of making the article comprises the steps of providing the GaAs-based semiconductor body (typically a semi-insulating GaAs substrate with a layer of epitaxial doped GaAs thereon), with at least a portion of the surface of the epitaxial layer being essentially atomically clean and essentially atomically ordered, forming, in situ, the oxide layer on the essentially atomically clean and ordered surface; implanting at least one ion species through the oxide layer and the interface into the first conductivity type region; heating the substrate with the oxide layer thereon to a temperature effective for activating at least a major portion of the implanted ions, with the heating carried out such that essentially no defects of a type that is detectable by high resolution transmission electron microscopy (HR-TEM) are formed at the interface; providing a source contact, a drain contact and a gate contact of the MOS-FET; and subjecting the MOS-FET to a post-metallization anneal selected such that the MOS-FET is substantially free of a drain current/voltage hysteresis.
The forming step exemplarily comprises forming the oxide layer such that the oxide layer has overall composition GaxAyOz, as defined above.
In an exemplary embodiment of the method the oxide layer is formed by simultaneous deposition from two (or possibly more) deposition sources, with one of the sources containing Ga2O3 (typically in powder form), and the other containing an oxide of a stabilizer element (e.g., Gd2O3), typically also in powder form. In another exemplary embodiment the oxide layer is formed by deposition from a single deposition source containing an oxide of a stabilizer element, e.g., Gd2O3, or a Ga-Gd-oxide such as Gd3Ga5O12.
As those skilled in the art know, it is common practice in the field of GaAs-based devices to carry out heat treatments by rapid thermal annealing (RTA), since the long heating times used in furnace annealing xe2x80x9c. . . caused some undesirable effects, such as substrate-quality degradation and implanted-dopant diffusion.xe2x80x9d See Very High Speed Integrated Circuits: Gallium Arsenide LSI, especially Ch. 1, III, xe2x80x9cRapid Thermal Annealingxe2x80x9d, p. 27-28, and middle of p. 54, T. Ikoma, Editor, Vol. 29 of Semiconductors and Semimetals, Willardson and Beer. However, we have discovered that using RTA, for instance for implant activation, frequently results in formation of defects at the GaAs/oxide interface. We currently believe that these defects are at least partially responsible for the low device yield. We have also discovered heat treatments (involving relatively slow heating and/or cooling) that do not result in formation of the above referred to defects, such that it is now possible to manufacture with high yield GaAs-based MOS-FETs with excellent characteristics, including long lifetime and substantially no drain current hysteresis.